1) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and more particularly to a process of formed a resist pattern using a tri-tone partially transmitting phase shift reticle. The present invention relates also to a photolithography mask and more particularly to a tri-tone partially transmitting phase shift reticle used to form dual damascene openings.
2) Description of the Related Art
As the integration of semiconductors is enhanced, the dimensions of devices cannot supply enough area for interconnection. To match the requirements of the metal oxide semiconductor (MOS) devices with smaller dimensions, designs of multilevel interconnections such as dual damascene interconnects, are adapted in most of the integrated circuits (ICs). Normally, an inter-metal dielectric (IMD) layer is used to isolate two conductive layers. In the dual damascene interconnect, a via plug connects adjacent the conductive levels. The trench portion or line connects between points on the same metal level.
There are two conventional methods of fabricating a dual damascene opening having a via and an trench (interconnection). One is to fabricate a via and an interconnection in two steps. That is, a dielectric layer is formed on a metal layer first. Using an etching technique to form a via hole, and a via plug is formed by filling the via hole with conductive material. Another metal layer is formed and defined. An inter-metal dielectric layer is then deposited. Another method is to use damascene technique. A via and an interconnection is formed simultaneously. Two steps to define photo-resist are required in the conventional damascene technique.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering
U.S. Pat. No. 6,482,554 (Matsunuma) that shows a for a method for a dual damascene pattern comprising: exposing a two photoresist layers.
U.S. Pat. No. 5,906,910 (Nguyen et al.) shows a method for a dual damascene pattern comprising: exposing a photoresist layer using a mask.
U.S. Pat. No. 6,355,399b1 (Sajan et al.) shows a method for a dual damascene pattern comprising: exposing a single photoresist layer using a grey tone mask.
U.S. Pat. No. 6,242,344 (Koh et al.) shows a exposure process for a dual damascene process.
U.S. Pat. No. 5,753,417 (Ulrich) shows a dual damascenes process using multiple exposures of one photoresist layer.
However, these methods can be improved upon.